path: root/rv32
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* fwupdate: fix flags matchingH. Peter Anvin2022-09-022-2/+2
* fwupdate: support fw v2 format (multiversion) for OTA updatesH. Peter Anvin2022-09-023-27/+89
* rv32: add missing header fileH. Peter Anvin2022-08-191-0/+16
* fw: propagate board_info from ESP32 to FPGAH. Peter Anvin2022-08-1811-74/+224
* fw: add ability to write a board ID string in ESP flashH. Peter Anvin2022-08-182-3/+9
* rv32: put the symbols for I/O registers back inH. Peter Anvin2022-08-086-93/+5
* Consolidate firmware format definitions into common/fwimg.hH. Peter Anvin2022-06-224-32/+35
* Create a common directory for sources between esp32 and rv32H. Peter Anvin2022-06-0612-148/+67
* rv32: add single-byte esplink get/put functionsH. Peter Anvin2022-06-052-0/+48
* esplink: add ring buffer read/write functions to rv32 sideH. Peter Anvin2022-06-055-6/+116
* fwupdate: update esp32 when flashing from sdcardH. Peter Anvin2022-05-207-91/+124
* rv32: combine heap and disk cacheH. Peter Anvin2022-05-1914-100/+263
* esplink: change to 7 interrupt/status bits per directionH. Peter Anvin2022-05-181-0/+1
* time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABCesplinkH. Peter Anvin2022-05-175-9/+36
* esplink: fix handshake between ESP and FPGAH. Peter Anvin2022-05-142-4/+4
* Merge esplink work with mainlineH. Peter Anvin2022-05-145-13/+4
| * Better timezone handling; upload helper scriptsH. Peter Anvin2022-05-041-1/+1
* | WIP: ringbuffer system between ESP32 and FPGAH. Peter Anvin2022-05-138-40/+42
* rv32: rename fw.h -> common.h for consistencyH. Peter Anvin2022-05-0323-22/+22
* esplink: better error checking, test ESP -> FPGA write directionH. Peter Anvin2022-05-032-2/+2
* esplink: fix startup time race condition on ESP32 sideH. Peter Anvin2022-05-032-3/+2
* esplink: handle arbitrary byte ranges; allow ESP to query statusH. Peter Anvin2022-05-022-2/+2
* Have ESP issue a handshake interrupt; some common link codeH. Peter Anvin2022-05-026-23/+51
* ESP32 code for FPGA link; test code and fixesH. Peter Anvin2022-05-013-2/+12
* Implement FPGA <-> ESP32 communication pathH. Peter Anvin2022-05-018-9/+65
* esp32 firmware image with support for OTA updates of both FPGA and ESP32H. Peter Anvin2022-04-123-29/+56
* system.c: disable the 5 s testing startup delayH. Peter Anvin2022-02-282-2/+2
* update: .fw file is a single compressed container; simplify I/O codeH. Peter Anvin2022-02-286-510/+487
* update: encode version in the firmware files; better .rpf generationH. Peter Anvin2022-02-183-7/+14
* Full infrastructure for updating flash via JTAG SVFH. Peter Anvin2022-02-1813-223/+421
* update: get closer to a working JTAG update infrastructureH. Peter Anvin2022-02-1314-56/+606
* flash update: handle data from a memory buffer; add headerH. Peter Anvin2022-02-135-143/+318
* fpga: virtual JTAG interfaceH. Peter Anvin2022-02-072-1/+6
* spiflash.[ch]: a (hopefully) platform-independent SPI flash writerH. Peter Anvin2022-02-064-3/+745
* rv32: build zlibH. Peter Anvin2022-02-0629-0/+14125
* fpga: generate .xsvf filesH. Peter Anvin2022-02-061-3/+12
* Produce raw binary files with and without extra contentsH. Peter Anvin2022-02-061-1/+6
* v2boot: simple boot loader connecting ESP32-SPI to flash-SPIH. Peter Anvin2022-02-041-1/+1
* rv32/compiler.h: fix typo in __constfunc definitionH. Peter Anvin2022-02-041-1/+1
* Fix USB serial number generationH. Peter Anvin2022-02-023-32/+28
* fw: download SPI ROM ID and send to USB very early in executionH. Peter Anvin2022-02-024-73/+104
* max80: fix timing bug that affected code execution from SDRAMH. Peter Anvin2022-02-022-2/+20
* spirom: fix SPI ROM I/O and data downloadingH. Peter Anvin2022-02-026-16/+53
* Move date stamp generation to fpga build; record SDRAM checksumH. Peter Anvin2022-01-2810-1854/+86
* spirom: issue the right 1-bit command; update ufddos80.romH. Peter Anvin2022-01-274-8/+18
* spirom: implement 1-bit DMA modeH. Peter Anvin2022-01-272-2/+2
* Fix SDRAM checksum generationH. Peter Anvin2022-01-224-11/+11
* serial: simplify physical tty and make BREAK reset workH. Peter Anvin2022-01-228-1185/+1571
* usb: use showahead on the Rx FIFO, but not the Tx FIFOH. Peter Anvin2022-01-192-1256/+1269
* Fix false positive ABC-bus memory overrun timerH. Peter Anvin2022-01-184-1223/+1241