This is a peripheral device modelled after Zilog's Z80PIO.  It
diverges from the Z80PIO in the following ways, in order to make it
better suited for embedded implementation without the constraints of
physical pin count:

- The Z80PIO is a dual-port device, which in some conditions "borrow"
  pins (BSTB# and BRDY are sometimes used by port A), but otherwise
  the two ports are completely independent.  This implementations
  contains only one port; however, instantiating two to create a
  two-port module is trivial; including the pin-sharing behaviour of a
  Z80PIO (connect BSTB# to both A.BSTB_n and B.ASTB_n;
  assign BRDY = A.BRDY | B.ARDY).

- The pin names are consistent with the "A" port of the Z80PIO.  For
  the bidirectional busses D7..D0 and A7..A0 I have separated out the
  input and output sides as DI/DO and AI/AO since embedded
  applications usually do not use multidriver tristate busses.  The
  suffix _n is used for inverted signals (since neither Verilog nor
  VHDL allows # in symbol names.)

- The Z80PIO snoops the CPU data bus to recognize the RETI
  instruction.  Since this implementation doesn't use true shared
  busses, an additional input, RETI#, has been added; this is expected
  to be driven low by the CPU (or by additional logic plugged into the
  CPU input data bus) when executing the RETI instruction.

- The reset is not multiplexed onto the M1# pin like it is on the
  Z80PIO.  Instead, a RESET# input is provided.

- The output data bus (Do) is set to all ones at any time it wouldn't
  be driven by Z80PIO.  The intent is that all the data outputs can be
  AND'd together before sending to the CPU.