path: root/swpll.v
Commit message (Expand)AuthorAgeFilesLines
* swpll: break the NCO counter into 3-bit(!) chunks; parameterizeHEADmasterH. Peter Anvin2019-10-121-47/+80
* Even better parameters; proper ramstyle annotationsH. Peter Anvin2019-10-121-4/+8
* swpll: works reasonalby well now. Still some very small glitches...H. Peter Anvin2019-10-121-63/+99
* swpll: actually extract the hsync signals from the composite syncH. Peter Anvin2019-10-091-2/+58
* More timing optimizations. Now pass even hold constraints.H. Peter Anvin2019-10-091-6/+7
* Now meets timing with a 360 MHz video master clock!H. Peter Anvin2019-10-091-50/+144
* Implement Altera's recommendation of async-assert sync-deassert resetH. Peter Anvin2019-10-041-6/+12
* Implement a software PLL to generate a synchronized clock for videoH. Peter Anvin2019-10-021-0/+127