This is a project for the Altera NIOS Development Kit with an
AleaREP/Microtronix Lancelot daughtercard (see http://www.fpga.nl/).
It should be easy enough to recompile for other cards with a
CompactFlash socket and binary audio output, just reconfigure the pin

It plays music recorded on the CompactFlash card to the audio out;
currently it expects 44100 Hz 16-bit bigendian stereo sound to be
recorded; this is standard raw CD data.

There has been talk of an MP3 decoder on opencores.org; that could be
added too, of course.

My main goal in doing this was to test out the abilities of a digital
DAC.  The Lancelot card only has a single bit audio output per
channel, connected to a low-pass RC filter with a 3 dB cutoff of only
about 10 kHz.  The sound coming out of this design isn't stellar, but
it's definitely much better than you'd think.

Version 1 used a 12-bit PWM DAC, version 2 and 3 used a first-order
delta-sigma DAC clocked at 200 MHz, and version 4 uses a second-order
delta-sigma DAC clocked at 100 MHz.

The remaining noise is most likely due to the lack of an interpolation
filter during upsampling to 100 MHz, which results in pops.  Another
thing that would definitely be desirable would be to add an
equalization filter to compensate for the low cutoff frequency of the
analog RC filter on the board.  This would be quite easy to do in
Statix or in Cyclone II, using DSP blocks; unfortunately my board is a
Cyclone I (EP1C20), which has no DSP blocks.

Versions 1-3 were mono due to underrun problems.  This turned out to
be a very silly problem -- cf_power was left floating, which resulted
in the CF card running out of power, depending on the access rate.  It
also meant most CF cards didn't work at all, depending on the power

The meaning of the LEDs are as follows:

D0 - CF card RDY#
D1 - CF card WAIT#
D2 - MSB of left channel
D3 - MSB of right channel
D4 - Left channel bitstream (intensity-modulated with amplitude)
D5 - Right channel bitstream (intensity-modulated with amplitude)
D6 - Data request
D7 - FIFO loaded

7seg - FIFO fill level (00 = empty, FF = full)