|author||H. Peter Anvin <firstname.lastname@example.org>||2007-01-30 07:02:18 +0000|
|committer||H. Peter Anvin <email@example.com>||2007-01-30 07:02:18 +0000|
2 files changed, 23 insertions, 16 deletions
@@ -1,8 +1,8 @@
-This is a project for the Altera NIOS Development Kit, Cyclone
-Edition, with an AleaREP Lancelot daughtercard (see
-http://www.fpga.nl/). It should be easy enough to recompile for other
-cards with a CompactFlash socket and binary audio output, just
-reconfigure the pin list.
+This is a project for the Altera NIOS Development Kit with an
+AleaREP/Microtronix Lancelot daughtercard (see http://www.fpga.nl/).
+It should be easy enough to recompile for other cards with a
+CompactFlash socket and binary audio output, just reconfigure the pin
It plays music recorded on the CompactFlash card to the audio out;
currently it expects 44100 Hz 16-bit bigendian stereo sound to be
@@ -13,7 +13,7 @@ added too, of course.
My main goal in doing this was to test out the abilities of a digital
DAC. The Lancelot card only has a single bit audio output per
-channel, connected to a low-pass filter with a 3 dB cutoff of only
+channel, connected to a low-pass RC filter with a 3 dB cutoff of only
about 10 kHz. The sound coming out of this design isn't stellar, but
it's definitely much better than you'd think.
@@ -21,18 +21,19 @@ Version 1 used a 12-bit PWM DAC, version 2 and 3 used a first-order
delta-sigma DAC clocked at 200 MHz, and version 4 uses a second-order
delta-sigma DAC clocked at 100 MHz.
-I suspect most of the remaining noise is due to the analog circuitry,
-and the low cutoff of the low-pass filter on this board.
+The remaining noise is most likely due to the lack of an interpolation
+filter during upsampling to 100 MHz, which results in pops. Another
+thing that would definitely be desirable would be to add an
+equalization filter to compensate for the low cutoff frequency of the
+analog RC filter on the board. This would be quite easy to do in
+Statix or in Cyclone II, using DSP blocks; unfortunately my board is a
+Cyclone I (EP1C20), which has no DSP blocks.
Versions 1-3 were mono due to underrun problems. This turned out to
be a very silly problem -- cf_power was left floating, which resulted
-in the CF card running out of power, depending on the access rate.
-On a chip with DSP blocks it might be possible to get better
-high-frequency response by applying a preemphasis filter; I haven't
-explored that since my FPGA is a Cyclone (EP1C20) and doesn't have DSP
-blocks. It also would increase the resource requirements hugely --
-this design currently takes less than 400 LE.
+in the CF card running out of power, depending on the access rate. It
+also meant most CF cards didn't work at all, depending on the power
The meaning of the LEDs are as follows:
@@ -10,8 +10,14 @@
* low pass filter.
+// The number of extra bits of precision (XBITS) necessary isn't very
+// clear. I ran the contents of a full CD through a simulator of the
+// algorithm, and came up with at least one transition which required
+// 6 extra bits.
`define MSB (BITS-1)
-`define XBITS 4 // Additional bits of precision
+`define XBITS 6 // Additional bits of precision
`define DBITS (`MSB+`XBITS)