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authorH. Peter Anvin <hpa@zytor.com>2022-11-07 10:03:45 -0800
committerH. Peter Anvin <hpa@zytor.com>2022-11-07 10:06:58 -0800
commita05ca7db68fc631acf445245defe42625e172ef9 (patch)
tree57006165d2406a02518fb99214b2e6be6eea762f
parenteebdba7d5514b977dca2cde5f430777f330a57f8 (diff)
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nasm-2.15.xx.zip
x86/insns.dat: fix VCVTNEPS2BF16nasm-2.15.xx
The VCVTNEPS2BF16 instruction was incorrectly specified as VCVTNE2S2BF16. Fortunately, the correct opcode for the latter was specified first, so it would emit the correct result when that instruction was specified. Fixes: https://bugzilla.nasm.us/show_bug.cgi?id=3392821 Reported-by: Agner <agner@agner.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--x86/insns.dat8
1 files changed, 4 insertions, 4 deletions
diff --git a/x86/insns.dat b/x86/insns.dat
index 71f626dc..4d02cbc7 100644
--- a/x86/insns.dat
+++ b/x86/insns.dat
@@ -1,6 +1,6 @@
;; --------------------------------------------------------------------------
;;
-;; Copyright 1996-2020 The NASM Authors - All Rights Reserved
+;; Copyright 1996-2022 The NASM Authors - All Rights Reserved
;; See the file AUTHORS included with the NASM distribution for
;; the specific copyright holders.
;;
@@ -6035,9 +6035,9 @@ XSUSLDTRK void [ f2 0f 01 e8] TSXLDTRK,FUTURE
VCVTNE2PS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
VCVTNE2PS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.256.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
VCVTNE2PS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.512.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
-VCVTNE2PS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
-VCVTNE2PS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.256.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
-VCVTNE2PS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.512.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.256.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.512.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
VDPBF16PS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 52 /r] AVX512BF16,FUTURE
VDPBF16PS ymmreg|mask|z,ymmreg*,ymmrm128|b32 [rvm:fv: evex.256.f3.0f38.w0 52 /r] AVX512BF16,FUTURE
VDPBF16PS zmmreg|mask|z,zmmreg*,zmmrm128|b32 [rvm:fv: evex.512.f3.0f38.w0 52 /r] AVX512BF16,FUTURE